1. Field of the Invention
The present invention relates to an integrated circuit device including a circuit for outputting an internal clock signal which has a predetermined phase relationship with a received clock signal. In particular, the present invention relates to an integrated circuit device which includes an internal clock output circuit for performing at high speed a mode switch from a low power consumption mode to a normal mode.
2. Related Arts
Recently the attention has been drawn to a synchronous DRAM (SDRAM), as a dynamic random access memory (DRAM) operating in synchronization with a system clock. An SDRAM receives and stores signals, such as addresses, data or commands, and reads and outputs data signals in synchronized with an external clock output by a system, so that a high speed operation is possible.
As the processing speed of an SDRAM is increased, the phase of an internal clock, which is generated by internally fetching an external clock, is shifted relative to the external clock. Thus, an internal clock signal may not be employed as a strobe signal for receiving the address signal, the data signal or the command signal, or for outputting an output data signal.
To compensate for the phase shifting, a delay locked loop circuit (hereinafter referred to simply as a DLL circuit), for example, generates an internal clock, which is synchronized and in phase with the external clock or so that its phase differs from that of the external clock by a predetermined amount. Then, the input address signal and another signals are fetched and a data signal is output at the timing for the internal clock.
The increase in the speed of the clock increases the frequency at which data is written to and read from the SDRAM and results in an increase in the power consumed by the SDRAM. Therefore, a low power consumption mode is provided for halting the internal operation of the SDRAM when no access is being performed. In the low power consumption mode, a clock enable signal is rendered inactive (level L) so as to inhibit the fetching of an external clock signal at an input buffer and to halt all unneeded internal operations.
FIG. 7 is a diagram illustrating the arrangement of a conventional internal clock output circuit provided for an SDRAM. An external clock signal E-CLK is transmitted to an input buffer 90, and its waveform is shaped to obtain a clock signal I-CLK. A phase difference that corresponds to the delay time for the input buffer 90 occurs between the clock signal I-CLK and the external clock signal E-CLK.
The clock signal I-CLK is transmitted to a DLL circuit 91. The DLL circuit 91 transmits as a strobe signal an internal clock signal CLK, which is synchronized and in phase with the external clock signal E-CLK, to an address buffer (not shown). The external clock signal E-CLK is also transmitted to a small buffer 92, and the small buffer 92 outputs a clock signal S-CLK, which is a data fetch signal for a CKE command latch circuit 94.
The clock enable signal CKE is a signal used for determining whether an external clock signal E-CLK should be fetched. The clock enable signal CKE is transmitted to an input buffer 93 and is changed to a clock enable signal CKE1, which is then output to a CKE command latch circuit 94. The CKE command latch circuit 94 fetches the clock enable signal CKE1 at the rising edge of the clock signal S-CLK, and generates a clock output control signal N1 for providing to the input buffer 90 as a strobe signal.
The input buffer 90 is rendered inactive when the clock output control signal N1 goes to level L and halts the output of the clock signal I-CLK. When the transmission of the clock signal I-CLK is halted, the DLL circuit 91 halts the output of the internal clock signal CLK. As a result, all internal operations are halted and the mode of the SDRAM is switched to the low power consumption mode.
However, when in the low power consumption mode, the input buffer 90 is rendered inactive and the fetching of the external clock signal E-CLK is inhibited, the feedback operation of the DLL circuit 91 is also halted. Once a DLL circuit 91 has been halted in the low power consumption mode, when returning to the normal mode, an extended period of time is required for the DLL circuit 91 to shift from the unlocked state to the locked state, and writing to and reading from the SDRAM can not be performed during this shifting period.
As the speed of an SDRAM is increased, an active power-down mode is necessary in which the operation of the DLL circuit 91 continues, even in the low power consumption mode, but the partial internal operation of the SDRAM is halted. The locked state of the DLL circuit is maintained in the active power-down mode, and when the mode of the SDRAM is switched to the normal mode, a normal operation can be initiated quickly. In this case, if the fetching of the external clock signal E-CLK in the input buffer 90 is halted, accordingly, the DLL circuit 91 is halted, and this is not preferable.
The clock enable signal CKE for shifting the system mode to the low power consumption mode is generated asynchronously with the external clock signal E-CLK, and is transmitted to the internal clock output circuit. Therefore, the falling and the rising edge timings of the clock output control signal N1, which is generated by the CKE command latch circuit 94, are unsynchronized with those of the internal clock signal CLK output by the DLL circuit 91.
Therefore, at the power down entry time, whereat the mode is switched from the normal to the low power consumption mode, and at the power down eject time, whereat the mode is switched from the low power consumption mode to the normal mode, the internal clock signal CLK having a width smaller than a predetermined pulse width would be output depending on the input timing of the clock enable signal CKE.
When the internal clock signal CLK without having the predetermined pulse width is provided into the SDRAM, a normal operation of SDRAM based on the internal clock signal CLK having the predetermined pulse width can not be preformed so that a reliability is deteriorated.